Programme Content
This module focuses on the analysis and design of digital CMOS circuits, including logic gates, combinational and sequential blocks at the transistor level.
CMOS ASIC Design Flow
MOS Device Physics
CMOS Inverter
Combinational and Sequential Logic Gates
This module covers creating a LINUX environment and introduces scripting languages to automate VLSI design, verification, and physical design flows.
Introduction to Linux
Scripting VLSI
VLSI Design Flow
RTL Coding and Design Styles
This module covers the transformation of RTL designs into optimized gate-level netlists using logic synthesis techniques. It also focuses on Static Timing Analysis to ensure timing closure.
Logic Synthesis Concepts and Optimization
Static Timing Analysis and Timing Concepts
Power-Aware Synthesis
This module focuses on incorporating test structures such as scan, ATPG, and BIST to improve fault coverage and manufacturability of digital ICs.
Scan Chain Insertion, ATPG & BIST
Fault Models and Fault Coverage Metrices
Soft Errors, Reliability & Resilience in Nano-Scale VLSI
This module introduces the backend implementation flow of digital ICs, including floorplanning, placement, clock tree synthesis, routing, and physical verification.
Floor planning, Placement and Routing
CTS and Power Planning
Advanced Node Challenges: FinFET, EUV Lithography, Double Patterning.
This module covers low-power design methodologies such as clock gating, multi-Vt, multi-voltage, and power gating techniques. It also introduces advanced design strategies to optimize power, performance, and area.
Low Power Design Methodologies
Sources of Power Dissipation
UPF/CPF for Power-Aware Design
This module introduces the fundamentals of mixed-signal and analog-mixed signal (AMS) design, focusing on the integration of analog and digital blocks on a single chip. It covers basic analog building blocks, interface circuits, and verification challenges in mixed-signal systems.
Introduction to Analog IC Design
PLL & Clock Generation Circuits
Mixed Signal Design
This module covers the fundamentals of IC packaging, including wire bond, flip-chip, and advanced packaging technologies. It focuses on electrical, thermal, and mechanical considerations that impact performance, reliability, and system integration.
Scan Chain Insertion, ATPG & BIST
Fault Models and Fault Coverage Metrices
Soft Errors, Reliability & Resilience in Nano-Scale VLSI
This will help students to apply theoretical concepts to real-world VLSI design projects and problem-solving scenarios. It helps develop practical skills, EDA tool proficiency, and confidence through Hands on learning.
Project 1: Combinational and Sequential CMOS Circuit Design
This project focuses on transistor-level design of CMOS combinational and sequential circuits such as logic gates and flip-flops. It emphasizes functional verification along with analysis of delay, power, and noise margins using CMOS design principles and simulations.
Project 2: Low Power I/O Circuit Design
This project focuses on the design of low-power CMOS I/O circuits such as input buffers, output drivers, and level shifters. It emphasizes power reduction techniques while ensuring signal integrity, speed, and reliable interfacing between different voltage domains.
Project 3: Power Management IC (PMIC) Design
This project involves the design and analysis of key PMIC blocks such as voltage regulators, references, and power switches for efficient power delivery. It focuses on achieving high efficiency, stability, and reliability under varying load and supply conditions.
Project 4: Clock Tree Synthesis and Static Timing Analysis
This project focuses on designing an efficient clock tree to achieve minimal skew and latency across the chip. It also involves performing Static Timing Analysis to ensure setup and hold timing closure under different process, voltage, and temperature conditions.
Project 5: Design for Test (DFT) and Automatic Test Pattern Generation
This project focuses on implementing DFT techniques such as scan insertion and test architectures to improve testability of digital designs. It also involves generating and analyzing ATPG patterns to achieve high fault coverage and ensure manufacturable, test-ready ICs.
Note: The list of projects is indicative and may be modified at the discretion of the Programme Coordinator as per programme requirements.
